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received characters are transferred to the CPU via the RxFIFO. In
station. The slave stations, with receivers that are normally disabled,
either case, the data bits are loaded into the data FIFO while the
examine the received data stream and wakeup the CPU (by setting
A/D bit is loaded into the status FIFO position normally used for
RxRDY)only upon receipt of an address character. The CPU
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
compares the received address to its station address and enables
break detect operate normally whether or not the receive is enabled.
the receiver if it wishes to receive the subsequent data characters.
1999 May 07 19
Philips Semiconductors Product specification
3.3V 5.0V Dual Universal Asynchronous
SC28L92
Receiver/Transmitter (DUART)
Each channel has 3 mode registers (MR0, 1, 2) which control the
PROGRAMMING
basic configuration of the channel. Access to these registers is
The operation of the DUART is programmed by writing control words
controlled by independent MR address pointers. These pointers are
into the appropriate registers. Operational feedback is provided via
set to 0 or 1 by MR control commands in the command register
status registers which can be read by the CPU. The addressing of
Miscellaneous Commands . Each time the MR registers are
the registers is described in Table 1.
accessed the MR pointer increments, stopping at MR2. It remains
The contents of certain control registers are initialized to zero on
pointing to MR2 until set to 0 or 1 via the miscellaneous commands
RESET. Care should be exercised if the contents of a register are
of the command register. The pointer is set to 1 on reset for
changed during operation, since certain changes may cause
compatibility with previous Philips Semiconductors UART software.
operational problems.
Mode, command, clock select, and status registers are duplicated
For example, changing the number of bits per character while the
for each channel to provide total independent operation and control.
transmitter is active may cause the transmission of an incorrect
Refer to Table 2 for register bit descriptions. The reserved registers
character. In general, the contents of the MR, the CSR, and the
at addresses H 02 and H 0A should never be read during normal
OPCR should only be changed while the receiver(s) and
operation since they are reserved for internal diagnostics.
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Table 1. SC28L92 register addressing READ (RDN = 0), WRITE (WRN = 0)
0 0 0 Mode Register A (MR0A, MR1A, MR2A) Mode Register A (MR0A, MR1A, MR2A)
0 0 0 1 Status Register A (SRA) Clock Select Register A (CSRA)
0 0 1 0 Reserved Command Register A (CRA)
0 0 1 1 Rx Holding Register A (RxFIFOA) Tx Holding Register A (TxFIFOA)
0 0 0 Input Port Change Register (IPCR) Aux. Control Register (ACR)
1
0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
0 1 0 Counter/Timer Upper (CTU) C/T Upper Preset Register (CTPU)
1
0 1 1 Counter/Timer Lower (CTL) C/T Lower Preset Register (CTPL)
1
1 0 0 0 Mode Register B (MR0B, MR1B, MR2B) Mode Register B (MR0B, MR1B, MR2B)
1 0 0 1 Status Register B (SRB) Clock Select Register B (CSRB)
1 1 0 Reserved Command Register B (CRB)
1 1 1 Rx Holding Register B (RxFIFOB) Tx Holding Register B (TxFIFOB)
1 0 0 Interrupt vector (68K mode) Interrupt vector (68K mode)
1
1 0 0 General purpose register (Intel mode) General purpose register (Intel mode)
1
1 1 0 1 Input Port (IPR) Output Port Conf. Register (OPCR)
1 1 1 0 Start Counter Command Set Output Port Bits Command (SOPR)
1 1 1 1 Stop Counter Command Reset output Port Bits Command (ROPR)
NOTE:
1. The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)
These are support functions for both Channels
The following named registers are the same for
Channels A and B
Input Port Change Register IPCR R
Mode Register MRnA MRnB R/W
Auxiliary Control Register ACR W
Status Register SRA SRB R only Interrupt Status Register ISR R
Interrupt Mask Register IMR W
Clock Select CSRA CSRB W only
Counter Timer Upper Value CTU R
Command Register CRA CRB W only
CTL R
Counter Timer Lower Value
Receiver FIFO RxFIFOA RxFIFOB R only
Counter Timer Preset Upper CTPU W
Transmitter FIFO TxFIFOA
TxFIFOB W only
Counter Timer Preset Lower CTPL W
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